There are a number of different types of analog to digital converters (ADC) including switched capacitance sigma delta (SC-SD) ADCs and continuous time sigma delta (CT-SD) ADCs. SC-SD ADCs are more commonly used, however, CT-SD ADCs are becoming more popular due to power and area constraints. CT-SD ADCs are oversampled ADCs that are designed to operate with input signals that have relatively low bandwidth (e.g. 200 kHz). The input signal is sampled within the CT-SD ADC at a frequency that is much higher (e.g. 50-100 times higher) than the signal bandwidth. This has the effect that the transfer function is close to one and the quantization error is shaped such that it is very small within the signal bandwidth but is much larger at higher frequencies. This allows the quantization error to be removed by filtering.
A CT-SD ADC comprises a modulator followed by a decimation filter. The modulator in a single order CT-SD ADC comprises a single integrator stage, but by adding further integrator stages (into the modulator), to produce a higher order CT-SD ADC, the gain can be increased and the quantization noise attenuated further in the signal bandwidth.
The embodiments described below are not limited to implementations which solve any or all of the disadvantages of known CT-SD ADCs.